DS3105LN+【PDF 37/124 页】IC TIMING LINE CARD 64-LQFP

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Sheet目录1994

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DS3105

2

Table of Contents

STANDARDS COMPLIANCE ....................................................................................................... 6

APPLICATION EXAMPLE ............................................................................................................ 7

BLOCK DIAGRAM ........................................................................................................................ 8

DETAILED DESCRIPTION............................................................................................................ 9

DETAILED FEATURES............................................................................................................... 11

INPUT CLOCK FEATURES ............................................................................................................ 11

T0 DPLL FEATURES................................................................................................................... 11

T4 DPLL FEATURES................................................................................................................... 11

OUTPUT APLL FEATURES........................................................................................................... 12

OUTPUT CLOCK FEATURES ......................................................................................................... 12

GENERAL FEATURES .................................................................................................................. 12

PIN DESCRIPTIONS ................................................................................................................... 13

FUNCTIONAL DESCRIPTION .................................................................................................... 18

OVERVIEW ................................................................................................................................. 18

DEVICE IDENTIFICATION AND PROTECTION ................................................................................... 19

LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION ........................................................... 19

INPUT CLOCK CONFIGURATION.................................................................................................... 19

Signal Format Configuration ................................................................................................................ 19

Frequency Configuration...................................................................................................................... 20

INPUT CLOCK MONITORING ......................................................................................................... 21

Frequency Monitoring .......................................................................................................................... 21

Activity Monitoring ................................................................................................................................ 21

Selected Reference Activity Monitoring ............................................................................................... 22

INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING .................................................................. 22

Priority Configuration............................................................................................................................ 22

Automatic Selection Algorithm ............................................................................................................. 23

Forced Selection .................................................................................................................................. 23

Ultra-Fast Reference Switching ........................................................................................................... 24

External Reference Switching Mode.................................................................................................... 24

Output Clock Phase Continuity During Reference Switching .............................................................. 24

DPLL ARCHITECTURE AND CONFIGURATION ................................................................................ 25

T0 DPLL State Machine ....................................................................................................................... 26

T4 DPLL State Machine ....................................................................................................................... 29

Bandwidth ............................................................................................................................................ 29

Damping Factor.................................................................................................................................... 30

Phase Detectors................................................................................................................................... 30

Loss-of-Lock Detection ........................................................................................................................ 31

Phase Build-Out ................................................................................................................................... 31

Input to Output (Manual) Phase Adjustment........................................................................................ 32

Phase Recalibration ............................................................................................................................. 32

Frequency and Phase Measurement................................................................................................... 33

Input Jitter Tolerance ........................................................................................................................... 34

Jitter Transfer ....................................................................................................................................... 34

Output Jitter and Wander ..................................................................................................................... 34

OUTPUT CLOCK CONFIGURATION ................................................................................................ 35

Signal Format Configuration ................................................................................................................ 35

Frequency Configuration...................................................................................................................... 35

FRAME AND MULTIFRAME ALIGNMENT.......................................................................................... 44

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